Microfluidic-method-processed p-type NiOx Thin-film Transistors

doi:10.15541/jim20180167

Abstract

Abstract:

It’s essential to develop patterning deposition methods to simplify the process of device fabrication and then reduce the production cost. In this work, a new patterning deposition method, i.e. microfluidic method, was demonstrated in details. In this technology, a micro-fluidic channel with a width of 80 μm and a height of 2 μm can be constructed between PDMS modules and substrates, and under capillary force precursor drops will move through the channel to form a patterned liquid film which is then fixed on the substrate via thermal treatments, and finally patterned films are prepared. In addition, the thermal-driven solidification process from NiO_x precursor powder to oxide was investigated through thermogravimetric/differential thermal analysis (TG-DTA) measurement. And the evolution of phase structure of the NiO_x precursor powder was analyzed with respect to post-annealing temperatures. Finally, thin-film transistors were fabricated applying the patterned NiO_x thin films as channels, and the optimized device showed typical p-type transistor features, with a field-effect mobility up to 0.8 cm²·V^-1·s^-1.

Key words: oxide semiconductors, solution method, wettability, thin-film transistors, TG-DTA curves

CLC Number:

TN321
TB43

LIANG Yu, LIANG Ling-Yan, WU Wei-Hua, PEI Yu, YAO Zhi-Qiang, CAO Hong-Tao. Microfluidic-method-processed p-type NiO_x Thin-film Transistors[J]. Journal of Inorganic Materials, 2019, 34(1): 79-84.

Figures/Tables 6

Fig. 1 Illustration of the preparation process of PDMS moulds

Fig. 2 Illustration of the patterning process by capillary method

Fig. 3 Thermogravimetric and differential thermal analysis (TG-DTA) curves of NiO precursor

Fig. 4 XRD patterns of NiO powders

Fig. 5 (a) Optical microscope image of a substrate patterned with NiO stripes with inset showing a close-up view; (b) Height fluctuation across the NiO stripe margin obtained by atomic force microscopy

Fig. 6 Schematic structure of the fabricated TFT device (a), output curves of the TFTs annealed at 300℃ (b) and 350℃ (c), and transfer curves of the corresponding TFTs (d)

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