Dual-gate IGZO-based Neuromorphic Transistors with Stacked Al2O3/Chitosan Gate Dielectrics

doi:10.15541/jim20220767

Abstract

Abstract:

Indium-gallium-zinc-oxide (IGZO)-based electric-double-layer (EDL) transistors have great applications for neuromorphic perception and computing systems because of their low processing temperature, high homogeneity, and plentiful ionic dynamics. However, IGZO-based EDL transistors have problems of high leakage current (>10 nA), high energy consumption and abnormal current spikes, which are the main obstacles to the development of neuromorphic computing systems based on such devices. In this work, a novel IGZO neuromorphic transistor with Al₂O₃/chitosan stacked gate dielectric was proposed. Compared with the monolayer chitosan gate dielectric transistor, the device with Al₂O₃/chitosan layer showed low subthreshold swing of 78.3 mV/decade, a low gate leakage current of 1.3 nA (reduced by about 98%), a large hysteresis window of 3.73 V (increased by about 3.4 times), a low excitable postsynaptic current of 0.86 nA (decreased by about 97%) and an energy consumption of 1.7 pJ for a spike event (0.5 V, 20 ms). Additionally, the emulation of spiking synaptic function and the synergistically modulation of the channel current were also realized, and the abnormal current spike caused by high leakage in synaptic plasticity simulation was also effectively avoided. The results suggest that the inserting of high-k dielectric layer can effectively improve the leakage current, energy consumption and performance of neuromorphic devices, which has substantial value for future ultra-low energy consumption neuromorphic perception and computing systems.

Key words: neuromorphic device, IGZO-based transistor, artificial synapse, stacked gate dielectric, high-k dielectric, synaptic plasticity

CLC Number:

TN321

WANG Jingyu, WAN Changjin, WAN Qing. Dual-gate IGZO-based Neuromorphic Transistors with Stacked Al₂O₃/Chitosan Gate Dielectrics[J]. Journal of Inorganic Materials, 2023, 38(4): 445-451.

Figures/Tables 8

Fig. 1 Schematic diagram of the IGZO-based neuromorphic transistor with different gate dielectrics (a) Chitosan gate dielectric; (b) Stacked Al2O3/chitosan gate dielectrics

Fig. 2 Leakage current curves and corresponding AFM images (inset) of monolayer gate dielectric and bilayer gate dielectric (a) Chitosan solid dielectric; (b) Stacked Al2O3/chitosan bilayer gate dielectric (Inset: AFM image of Al2O3 membrane)

Fig. 3 Transfer characteristics and output characteristics of two kinds of dielectric devices (a,b) Transfer characteristics of chitosan dielectric device (a) and stacked Al2O3/chitosan bilayer gate dielectric device (b); (c) Output characteristic of chitosan dielectric device; (d) Output characteristic of stacked Al2O3/chitosan bilayer gate dielectric device

Table 1 Transistor parameters of IGZO-based transistors

Gate dielectric	I_off	I_on/I_offratio	Subthreshold swing/ (mV·decade^-1)	Hysteresis window/V	Leakage current (V_G=1.8 V)/nA	μ_sat/ (cm²·V^-1·s^-1)
Chitosan	2.92×10^-9	1.06×10⁵	98.8	1.10	66.4	18.0
Chitosan/Al₂O₃	4.20×10^-11	2.20×10⁶	78.3	3.73	1.3	20.9

Fig. 4 (a) Top micrograph, (b) transfer characteristics with different VG2 (from-2.0 V to 1.0 V) and (c) the Vth with different VG2 of transistor

Fig. 5 (a) Schematic diagram of biological synapse and their equivalent electrical circuit of the neuromorphic transistor, (b) EPSC responses under an electric pulse of 0.5 V, and (c) EPSC induced by electric pulses of different amplitudes for IGZO-based dual-gate transistor with stacked Al2O3/chitosan gate dielectrics

Table 2 Energy consumption of the single EPSC peak in different artificial synaptic transistors

Structure	V_DS/V	V_G pulse	EPSC/nA	Energy consumption/(pJ·spike^-1)	Ref.
Nanogranular SiO₂/IZO	1.0	0.8 V, 20 ms	5000	10⁵	[33]
GO+Chitosan/IGZO	0.1	0.5 V, 20 ms	14	28	[34]
Carbon Nanotube (CNT)	0.5	4.0 V, 1.0 ms	15	7.5	[35]
Chitosan/IZO	0.1	0.5 V, 25 ms	2.6	6.5	[36]
Chitosan/IWO	0.1	0.2 V, 20 ms	4.7	9.4	[37]
Chitosan/IGZO	0.1	0.5 V, 20 ms	26	52	[38]
Tungsten oxide	0.3	0.6 V, 70 ms	3.8	79	[39]
Chitosan/ IGZO	0.1	0.5 V, 20 ms	24	48	This work
Chitosan/Al₂O₃/IGZO	0.1	0.5 V, 20 ms	0.86	1.7	This work

Fig. 6 (a) Multi-pulse facilitation induced by eight successive electric pulse (0.5 V, 25 ms) and (b) ratio of A8/A1 plotted as a function of the time interval between the pulses for IGZO-based dual-gate transistor with stacked Al2O3/chitosan gate dielectrics

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Dual-gate IGZO-based Neuromorphic Transistors with Stacked Al₂O₃/Chitosan Gate Dielectrics

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