Abstract:

In the post-Moore era, temporary bonding and ultra-thin wafer thinning of large-size functional wafers have emerged as essential technologies underpinning innovation within the semiconductor industry. However, challenges such as wafer warpage and breakage commonly encountered during wafer thinning severely limit device performance and yield. To address these issues, WAN’s group at Yongjiang Laboratory developed a cost-effective, room-temperature ultra-flat temporary bonding technique. This innovative process has significantly reduced the risk of wafer warpage while achieving high flatness and stability in wafer bonding. By integrating this process with domestically developed thinning equipment, the group successfully thinned 8-inch silicon wafers down to 8 µm, 12-inch silicon power chips to 15 µm with a total thickness variation (TTV) ≤2 µm, and 8-inch lithium niobate wafers to 8-10 µm, thereby satisfying diverse piezoelectric micro-electro-mechanical system (MEMS) application demands. Currently, this technology is widely applied in heterogeneous integration of various wafer materials, including silicon, lithium niobate/lithium tantalate, gallium oxide, and indium phosphide, providing crucial support for the localization and development of power chips and high-performance MEMS devices.

Key words: large-size wafer, temporary bonding and thinning, room temperature, ultra-flat