高级检索
无机材料学报

无机材料学报

• • 上一篇    下一篇

大尺寸功能晶圆临时键合与减薄

朱一新1,2, 喻志奎1, 万青1   

  1. 1.甬江实验室,宁波 315202;
    2.中国科学技术大学微电子学院,合肥 230026
  • 收稿日期:2025-06-06 修回日期:2025-06-18
  • 通讯作者: 万青,甬江实验室功能材料与器件异构集成研究中心主任,研究员. E-mail：qing-wan@ylab.ac.cn
  • 作者简介:朱一新(1994-),甬江实验室博士后. E-mail: yixin-zhu@ylab.ac.cn
  • 基金资助:
    浙江省自然科学基金(LMS25F040005); 浙江省引进培育领军型创新创业团队(2023TD1035); 浙江省重点研发计划资助项目(2024SSYS0043)

Large-size Functional Wafer Temporary Bonding and Thinning

ZHU Yixin1,2, YU Zhikui1, WAN Qing1   

  1. 1. Yongjiang Laboratory, Ningbo 315202, China;
    2. School of Microelectronics, University of Science and Technology of China, Hefei 230026, China
  • Received:2025-06-06 Revised:2025-06-18
  • Contact: WAN Qing, Professor and Director of Functional Materials & Devices Heterogeneous Integration Center at Yongjiang Laboratory. E-mail: qing-wan@ylab.ac.cn
  • About author:ZHU Yixin(1994–), Postdoctoral Researcher at Yongjiang Laboratory. E-mail: yixin-zhu@ylab.ac.cn
  • Supported by:
    Zhejiang Provincial Natural Science Foundation of China(LMS25F040005); Zhejiang Province Introduces and Cultivates Leading Innovation and Entrepreneurship Teams; Key R&D Program of Zhejiang (2024SSYS0043)

PDF (PC)

19

摘要： 在后摩尔时代,大尺寸功能晶圆临时键合与超薄减薄技术已成为半导体产业创新的重要支撑。然而,在晶圆减薄过程中,翘曲和破损等问题普遍存在,严重制约了器件性能与良率。针对上述挑战,本团队研发了一种低成本和室温超平整的临时键合工艺,有效降低了晶圆翘曲风险,实现了高平整度和高稳定性的晶圆键合。结合国产减薄设备,本团队成功实现了多项突破：将8英寸硅晶圆减薄至8 μm;12英寸硅功率芯片减薄至15 μm (总厚度变化TTV≤2 μm);8英寸铌酸锂减薄至8~10 μm,可满足多种压电MEMS需求。目前,该技术已成功应用于硅、铌酸锂/钽酸锂、氧化镓、磷化铟等多种晶圆体系的异质集成,为功率芯片和高性能MEMS器件的国产化进程提供了重要支撑。

关键词: 大尺寸晶圆, 临时键合与减薄, 室温, 超平整

Abstract: In the post-Moore era, temporary bonding and ultra-thin wafer thinning of large-size functional wafers have emerged as essential technologies underpinning innovation within the semiconductor industry. However, challenges such as wafer warpage and breakage commonly encountered during wafer thinning severely limit device performance and yield. To address these issues, WAN's group at Yongjiang Laboratory developed a cost-effective, room-temperature ultra-flat temporary bonding technique. This innovative process has significantly reduced the risk of wafer warpage while achieving high flatness and stability in wafer bonding. By integrating this process with domestically developed thinning equipment, the group successfully thinned 8-inch silicon wafers down to 8 µm, 12-inch silicon power chips to 15 µm with total thickness variation (TTV) ≤ 2 µm, and 8-inch lithium niobate wafers to 8-10 µm, thereby satisfying diverse piezoelectric MEMS application demands. Currently, this technology is widely applied in heterogeneous integration of various wafer materials, including silicon, lithium niobate/lithium tantalate, gallium oxide, and indium phosphide, providing crucial support for the localization and development of power chips and high-performance MEMS devices.

Key words: large-size wafer, temporary bonding and thinning, room temperature, ultra-flat

中图分类号: